发明名称 |
METHOD AND DEVICE FOR ARRANGING DUMMY PATTERN, PROGRAM, AND SEMICONDUCTOR DEVICE |
摘要 |
<p><P>PROBLEM TO BE SOLVED: To solve the problem wherein a load of OPC process (especially a load of bias process) increases under the optical effect following arrangement of a dummy pattern. <P>SOLUTION: A pattern arranging device 50 arranges a dummy pattern in a layout region where a plurality of wiring patterns are arranged. The pattern arranging device 50 is provided with: an arrangement region setting part 54 which sets the arrangement region where a dummy pattern is arranged in an intermediate region between the wiring patterns adjoining each other in such a way that distances from both adjoining wiring patterns are substantially constant; and a pattern arranging part 55 for arranging the dummy pattern in the arrangement region. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
申请公布号 |
JP2009049107(A) |
申请公布日期 |
2009.03.05 |
申请号 |
JP20070212360 |
申请日期 |
2007.08.16 |
申请人 |
NEC ELECTRONICS CORP |
发明人 |
KOBAYASHI HISAHIRO |
分类号 |
H01L21/82;G03F1/36;G03F1/70;G06F17/50;H01L21/3205;H01L21/768;H01L21/822;H01L23/52;H01L23/522;H01L27/04 |
主分类号 |
H01L21/82 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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