| 摘要 |
A method for fabricating a memory is provided. A tunneling dielectric layer, a first conductive layer, and a mask layer are formed on a substrate. The mask layer, the first conductive layer, the tunneling dielectric layer, and the substrate are patterned to form trenches in the substrate. A passivation layer and isolation structures are formed in sequence to fill the trenches, and the etching rate of the isolation structures is greater than that of the passivation layer. After the mask layer is removed, a second conductive layer is formed on the first conductive layer. Portions of the isolation structures are removed to expose the sidewalls of the first and the second conductive layers. Further, a third conductive layer is formed on the exposed sidewalls of the first and the second conductive layers. An inter-gate dielectric layer and a control gate are formed on the substrate.
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