发明名称 Design Method and System for Minimizing Blind Via Current Loops
摘要 A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via.
申请公布号 US2009031270(A1) 申请公布日期 2009.01.29
申请号 US20070829179 申请日期 2007.07.27
申请人 DOURIET DANIEL;HARIDASS ANAND;HUBER ANDREAS;WEEKLY ROGER D 发明人 DOURIET DANIEL;HARIDASS ANAND;HUBER ANDREAS;WEEKLY ROGER D.
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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