A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve readingand writing performance. One of the n-wells and p-wells can be globally biased. Error reduction and/or correction can be performed.
申请公布号
WO2009004535(A2)
申请公布日期
2009.01.08
申请号
WO2008IB52544
申请日期
2008.06.25
申请人
NXP B.V.;ELVIRA VILLAGRA, LUIS;MEIJER, RINZE, I., M.;PINEDA DE GYVEZ, JOSE, DE JESUS
发明人
ELVIRA VILLAGRA, LUIS;MEIJER, RINZE, I., M.;PINEDA DE GYVEZ, JOSE, DE JESUS