| 摘要 |
An integrated circuit (100) is disclosed comprising a plurality of circuit portions (130), each of the circuit portions having an internal supply rail (170) coupled to a global supply rail (160) via a cluster (140) of switches (152; 154) coupled in parallel between the internal supply rail (170) and the global supply rail (160). Each cluster (140) of switches (152; 154) has a first switch (152) having a first size and a second switch (154) having a second size, a fault-free first switch (152) having a higher resistance than a fault-free second switch (154). The IC (100) further comprises a test arrangement for testing the respective clusters (140) of switches (152; 154) in a test mode. The test arrangement comprises a test control input; a test output coupled to the respective internal supply rails (170) and control means (110, 114, 116) coupled to the test control input for enabling a selected cluster (140) of switches (152; 154) in the test mode. The control means comprise first selection means (114) for selectively enabling the first switch (152) and second selection means (116) for selectively enabling the second switch (154) of the selected cluster (140) in the test mode. This arrangement allows for the accurate measurement of the resistance of power switches (152; 154) between a global power rail (160) and an internal power rail (170) of a circuit portion (130), thus facilitating the detection of both resistive and stuck-at faults in these switches (152; 154).
|
