CACHE MEMORY DEVICE, ARITHMETIC PROCESSING UNIT, AND ITS CONTROL METHOD

摘要

A cache memory device is structured to include a data holding part including a plurality of ways having a plurality of cache lines, an alternating data register for holding data for one of the cache lines of the data holding part or for part of the cache lines, an alternating address register for holding index addresses indicating a defective cache line where a failure occurs in the data holding part and a failure occurrence part in the defective cache line, an alternating way register for holding information of a way containing the failure occurrence part, an address matching circuit for comparing an index address to be used for access whenthe data holding part is to be accessed with an index address of the alternating address register, and a way matching circuit for comparing way information to be used for the access when the data holding part is to be accessed with way information held by the alternating way register.