INFORMATION PROCESSOR, CACHE MEMORY CONTROLLER, AND MEMORY ACCESS SEQUENCE ASSURANCE METHOD

摘要

When the data on a cache RAM (21) is rewritten in the store processing of a thread, an address match judging circuit (25) searches a fetch port (22) for holding the requests for the other threads and checks to see if the processing is already completed, the data is a load-line instruction, and there is the request in which the target address of the instruction matches the target address of the store processing. If the request is detected, the address match judging circuit (25) sets an instruction reexecution request flag by the store to all the entries of the fetch port (22) from the next of an entry for holding the oldest request to an entry for holding the detected request. When the processing of the oldest request is performed, an instruction reexecution request circuit (26) transmits an instruction reexecution request for the request held in the entry in which the instruction reexecution request flag by the store is set to an instruction control unit (10). This assures the sequence property of the data update between threads in an SMT processor.