INFORMATION PROCESSOR AND LOAD ARBITRATION CONTROL METHOD

摘要

A simultaneous multi-thread type information processor and control method for qualitatively judging the load balance between threads and arbitrating the performance load balance between the threads. The simultaneous multi-thread type information processor comprising an instruction input control section for sharing a control of inputting an instruction to a computing section for acquiring the instruction from a memory and executing the computation based on the instruction between the threads, a commit stack entry provided for each thread for holding information in which the instruction is decoded, an instruction completion sequence control section for updating the memory and a general purpose register according to the result of the computation computed by the computing section in the sequence of the instruction inputted from the instruction input control section, and a performance load balance analyzing section for detecting the information registered in the commit stack entry and controlling the instruction input control section according to the result of the detection and the method for arbitrating and controlling the performance load between the threads.