| 摘要 |
Techniques for erasing memory devices of a flash memory array having a plurality of operative wordlines and at least one dummy wordline adjacent an end one of the operative wordlines are disclosed. Erasing the memory devices can include applying a gate voltage to the wordlines and applying a bias voltage to the dummy wordlines. In one arrangement, an electrical connection is established between the dummy wordline and the end one of the operative wordlines. |
