SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT DESIGN METHOD

摘要

PROBLEM TO BE SOLVED: To improve electromigration resistance of a semiconductor integrated circuit while suppressing an increase in chip area. SOLUTION: A cell VDD wiring 20 and a cell VSS wiring 21 are wired in parallel with each other so as to supply a current to a standard cell including logic cells 10, 11, and 12. An upper-layer VDD wiring 30 and an upper-layer VSS wiring 31 are wired in an upper layer than the cell VDD wiring 20 and the cell VSS wiring 21 perpendicularly to the cell VDD 20 wiring and the cell VSS wiring 21. The upper-layer VDD wiring 30 is connected with the cell VDD wiring 20 by a stacked via 40. The upper-layer VSS wiring 31 is connected with the cell VSS wiring 21 by a stacked via 40. The cell VDD wiring 20 has a wide part whose width is wider than that of a region not overlapping with the upper-layer VDD wiring 30 and the upper-layer VSS wiring 31 in a region being a region overlapping with the upper-layer VDD wiring 30 and including a part where the stacked via 40 is arranged. COPYRIGHT: (C)2008,JPO&INPIT