| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce a leak current, during a standby mode, of a flip-flop circuit, a latch circuit, etc. <P>SOLUTION: A flip-flop circuit 20 comprises a master latch circuit 1, a slave latch circuit 3, a clamp section 3, and a clock buffer circuit 4. The clamp section 3 is provided between a node N3 and a low potential side power source (ground potential) Vss and is constituted of an Nch MOS transistor NMT1 and a gate-grounded Nch MOS transistor NMT2. While the flip-flop circuit 20 is on standby, a standby signal STB of "Low" level is input to the gate of the Nch MOS transistor NMT1 in the clamp section 3, the Nch MOS transistor NMT1 is turned "OFF", the voltage of the node N3 is pulled up by a forward voltage (Vf) of the gate-grounded Nch MOS transistor NMT2, and the voltage of "Vdd-Vf" is applied to the master latch circuit 1. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
