| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for reducing increase in latency when an access conflict occurs in an external memory. <P>SOLUTION: The semiconductor integrated circuit comprises a memory controller connected to a control terminal and a data terminal for connecting to a memory, and first and second masters connected to the memory controller. The memory control uses one of a rising edge and a falling edge of a clock signal as a first edge and the other as a second edge, transmits a control signal corresponding to memory access by a first master and a control signal corresponding to memory access by a second master to the control terminal synchronously with the first and second edges individually, and inputs/outputs input/output data of the first master and that of the second master from/to the data terminal synchronously with the first and second edges individually. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
