发明名称 Method and system for reducing inter-layer capacitance in integrated circuits
摘要 The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.
申请公布号 US2008235643(A1) 申请公布日期 2008.09.25
申请号 US20080156281 申请日期 2008.05.30
申请人 LSI LOGIC CORPORATION 发明人 TARAVADE KUNAL N.;CALLAN NEAL;FILSETH PAUL G.
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址