发明名称 |
CONVERSION DEVICE, CONVERSION METHOD, PROGRAM, AND RECORDING MEDIUM |
摘要 |
Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device 400 converts a test vector set corresponding to the full scan sequential circuit. The conversion device 400 comprises a setting unit 402 for setting a candidate bit which can be a don't care bit and a fixed bit which cannot be the don't care bit according to predetermined constraint conditions based on an input-output relationship in the logic circuit in order to identify the don't care bit identifiable as don't care from each test vector of the test vector set, and a logic value deciding unit 404 for deciding a logic value for the don't care bit in view of a relationship in a plurality of bit pairs in relation to a test cube including the don't care bit identified by the setting unit 402.
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申请公布号 |
US2008235543(A1) |
申请公布日期 |
2008.09.25 |
申请号 |
US20080129746 |
申请日期 |
2008.05.30 |
申请人 |
JAPAN SCIENCE AND TECHNOLOGY AGENCY;KYUSHU INSTITUTE OF TECHNOLOGY;SYSTEM JD CO., LTD. |
发明人 |
WEN XIAOQING;KAJIHARA SEIJI;MIYASE KOHEI;MINAMOTO YOSHIHIRO;DATE HIROSHI |
分类号 |
G01R31/3177;G06F11/25 |
主分类号 |
G01R31/3177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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