| 摘要 |
<P>PROBLEM TO BE SOLVED: To enlarge a synchronization range by reducing a phase difference (a steady phase error) between the input signal and the output signal of a PLL circuit with the use of a simple means. <P>SOLUTION: The PLL circuit includes: a phase comparator for detecting the phase difference between a reference signal and a comparison signal; a loop filter; a voltage controlled oscillator for generating the output signal with a frequency corresponding to a control voltage; and a comparison signal generating circuit for feeding-back the comparison signal generated from the output signal to the phase comparator. Further, the PLL circuit has an error detection circuit for detecting the delay amount of the phase in the comparison signal with respect to the phase of the reference signal when synchronization in frequency is obtained between the reference signal and the comparison signal. For example, the comparison signal generating circuit delays the output signal in response to the delay amount, detected by the error detecting circuit, and feeds back the signal, delayed from the output signal, to the phase comparator as the comparison signal. <P>COPYRIGHT: (C)2008,JPO&INPIT |
