发明名称 Method of Forming Solder Bump on High Topography Plated Cu
摘要 A solder bump is formed on a high-topography, electroplated copper pad integrating a first and second passivation layer. A sacrifice layer is deposited over the second passivation layer. The sacrifice layer is lithographically patterned. A via is etched in the sacrifice layer. A solder bump is formed in the via. A portion of the sacrifice layer is removed using the solder bump as a mask. A semiconductor device includes a substrate, an input/output (I/O) pad disposed over the substrate, a first passivation layer disposed over a portion of the I/O pad, a first conductive layer disposed over the first passivation layer, a second passivation layer disposed over the first conductive layer, a sacrifice layer disposed over the second passivation layer, the sacrifice layer having a via, and a solder bump formed in the via, the solder bump used as a mask to remove a portion of the sacrifice layer.
申请公布号 US2008230902(A1) 申请公布日期 2008.09.25
申请号 US20070689282 申请日期 2007.03.21
申请人 STATS CHIPPAC, LTD. 发明人 LIN YAOJIAN;ZHANG QING;CAO HAIJING
分类号 H01L23/482;H01L21/60 主分类号 H01L23/482
代理机构 代理人
主权项
地址
您可能感兴趣的专利