| 摘要 |
A shift register and an image display apparatus including the same are provided to prevent reduction of driving capabilities of first and second pull down circuits by performing alternately discharge on the first and second pull down circuits. First and second clock terminals(CK1,CK2) receive clock signals having different phases. A first transistor(Q1) supplies a first clock signal, which is inputted to the first clock terminal, to an output terminal(OUT). A second transistor(Q2) discharges the output terminal. A third transistor(Q3) having a control terminal connected to a first input terminal(IN1) supplies a first voltage signal, which is inputted to a first voltage signal terminal(T1), to a first node connected to a control terminal of the first transistor. A fourth transistor(Q4) having a control terminal connected to a second input terminal supplies a second voltage signal, which is inputted to a second voltage signal terminal(T2), to the first node. First and second pull-down circuits(41,42) discharge the first node according to activation of first and second clock signals, respectively. The discharge of the first node performed by the first and second pull-down circuits is performed during a no charge period of the first node and not performed during a charge period of the first node.
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