Apparatus and method for correcting duty cycle of clock signal

摘要

An apparatus for correcting a duty cycle of an input clock signal to generate a digitally corrected clock signal includes a duty cycle detector, an analog duty cycle correcting unit, and a digital duty cycle correcting unit. The duty cycle detector generates a duty cycle signal indicating a respective duty cycle of the digitally corrected clock signal. The analog duty cycle correcting unit adjusts a current flowing through a node to adjust the respective duty cycle of the input clock signal for generating an analog corrected clock signal at the node. The digital duty cycle correcting unit adjusts the respective duty cycle of the analog corrected clock signal according to the duty cycle signal for generating the digitally corrected clock signal.