| 摘要 |
A synchronous semiconductor memory device including a data alignment reference pulse generating unit configured to generate a data alignment reference pulse in response to a data strobe signal (DQS), an alignment hold signal generating unit configured to generate an alignment hold signal, which is activated during a period corresponding to a postamble of the data strobe signal, in response to the data alignment reference pulse and a data input clock, and a data alignment unit configured to align input data in response to the data alignment reference pulse and the alignment hold signal.
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