发明名称 Method of forming an oxide isolated metal silicon-gate JFET
摘要 A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.
申请公布号 US7713804(B2) 申请公布日期 2010.05.11
申请号 US20080276574 申请日期 2008.11.24
申请人 SUVOLTA, INC. 发明人 VORA MADHUKAR B.;KAPOOR ASHOK K.
分类号 H01L21/337 主分类号 H01L21/337
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