| 摘要 |
A synchronous semiconductor device includes: input buffers; a latch-signal generating circuit that generates a latch signal based on a clock signal; latch circuits that latch an address signal in response to the latch signal; delay circuits that supply the latch circuits with the address signal in synchronism with the latch signal; NOR gate circuits that inactivate the address signal in response to a chip select signal becoming inactive, the NOR gate circuits being arranged between the input buffers and the delay circuits. According to the present invention, without stopping an operation of the input buffers or an internal clock signal, consumed power generated between the input buffers and the latch circuits can be effectively reduced.
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