| 摘要 |
Provided are a semiconductor integrated circuit (IC) including a pad for a wafer test and a method of testing a wafer including a semiconductor IC. The semiconductor IC includes a first address generator, a second address generator, and an address output unit. The first address generator generates a normal address having (M+N) bits or a first test address having M bits corresponding to voltages applied to a plurality of address pads. The second address generator generates a second test address having N bits corresponding to a voltage applied to an additional pad. Therefore, according to the semiconductor IC and the wafer test method, an additional pad is provided to generate an N-bit test address in wafer test mode such that the number of pads needed to test a device can be reduced. As a result, more semiconductor ICs can be tested simultaneously.
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