发明名称 |
Method and system for designing semiconductor circuit devices to reduce static power consumption |
摘要 |
A method and system are disclosed for designing a complex integrated electronic circuit architecture including a plurality of circuit portions integrated into a single chip structure. The method includes providing at least one library of cells with a variable channel length L; creating a layout of an integrated circuit using the cells with an initial channel length L; performing a timing analysis of the integrated circuit to analyze more and less critical paths by evaluating respective path delays; selecting a set of less critical paths to be modified; evaluating the leakage currents of the less critical paths of the selected set; and modifying the variable channel length L of the cells which are involved in the less critical paths of the selected set on the basis of the corresponding evaluated leakage current and the respective path delays, whereby a modified integrated circuit with a reduced circuit leakage current is obtained.
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申请公布号 |
US7716618(B2) |
申请公布日期 |
2010.05.11 |
申请号 |
US20070809783 |
申请日期 |
2007.05.31 |
申请人 |
STMICROELECTRONICS, S.R.L. |
发明人 |
FERRARI LINA;CRETTI FRANCESCO |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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