发明名称 Retention test system and method for resistively switching memory devices
摘要 A retention test system and method for resistively switching memory devices is disclosed. One embodiment provides a plurality of memory cells configured to be changed over between a first state of high electrical resistance and a second state of low electrical resistance, wherein the system is configured to apply a bias voltage to at least one memory cell of the memory device to be tested.
申请公布号 US7715258(B2) 申请公布日期 2010.05.11
申请号 US20070962956 申请日期 2007.12.21
申请人 QIMONDA AG;ALTIS SEMICONDUCTOR 发明人 SYMANCZYK RALF;ALBAREDE PAUL-HENRI
分类号 G11C29/00 主分类号 G11C29/00
代理机构 代理人
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