发明名称 Memory apparatus
摘要 A memory apparatus is provided that includes a storage element configured to store and retain information based on the state of an electric resistance, and a circuit element connected in series to the storage element as a load. In the memory apparatus, a resistance value is set to one of a plurality of different levels by controlling a voltage or a current applied to the circuit element or the storage element upon the writing. The storage element includes levels having low resistance values and levels having high resistance values obtained after erasing, to each of which different information is allocated. One storage element may store information having a ternary value or more. When erasing the information from the levels excluding the level having the lowest resistance value, a level is initially changed to the level having the lowest resistance value, and subsequently changed to that having a higher resistance value.
申请公布号 US7715220(B2) 申请公布日期 2010.05.11
申请号 US20070757107 申请日期 2007.06.01
申请人 SONY CORPORATION 发明人 TSUSHIMA TOMOHITO;ARATANI KATSUHISA
分类号 G11C11/00 主分类号 G11C11/00
代理机构 代理人
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