发明名称 Clustered variations-aware architecture
摘要 Methods and apparatus to provide a clustered variations-aware architecture are described. In one embodiment, one or more variations within a clock domain are detected and utilized to adjust a clock signal of the clock domain.
申请公布号 US7600145(B2) 申请公布日期 2009.10.06
申请号 US20050562189 申请日期 2005.10.26
申请人 INTEL CORPORATION 发明人 VERA XAVIER;ERGIN OGUZ;UNSAL OSMAN;GONZALEZ ANTONIO
分类号 G06F1/04 主分类号 G06F1/04
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