LDPC DECODING METHODS AND APPARATUS

摘要

A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than th e full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set o f control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.