发明名称 Net/wiring selection method, net selection method, wiring selection method, and delay improvement method
摘要 The present invention relates to a net/wiring selection method for selecting, from among nets/wirings wired on the basis of layout information, a net/wiring whose layout is to be changed with priority in order to improve a delay. To enable efficient elimination of a critical path, the method is arranged to include a wiring capacitance lower limit computation step for computing wiring capacitance lower limits on the basis of layout information; an inter-wiring capacitance computation step for computing, as an inter-wiring capacitance, a difference between a real wiring capacitance and the wiring capacitance lower limit; a parallel wiring length extraction step for extracting a parallel wiring length existing between adjacent wirings of the respective wirings; and a selection step for selecting a net/wiring whose layout is to be changed, on the basis of the inter-wiring capacitance, the parallel wiring length, and a slack value.
申请公布号 US7600205(B2) 申请公布日期 2009.10.06
申请号 US20060637728 申请日期 2006.12.13
申请人 发明人 IKEDA HIROSHI
分类号 G06F17/50;G06F9/45;H01L21/82 主分类号 G06F17/50
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