Power consumption reduction techniques for an RF receiver implementing a mixing DAC architecture

摘要

A receiver (100) includes a mixing digital-to-analog converter (DAC) (120), a direct digital frequency synthesizer (DDFS) (116), and a clock circuit (114). The mixing DAC (120) includes a radio frequency (RF) transconductance section (124) and a switching section (128). The RF transconductance section (124) includes an input configured to receive an RF signal. The switching section is coupled to the RF transconductance section (124) and includes inputs, configured to receive bits associated with a digital local oscillator (LO) signal, and an output. The DDFS (116) includes outputs, configured to provide the bits associated with the digital LO signal to the inputs of the switching section (128), and a first clock input, configured to receive a first clock signal that sets a sample rate for the digital LO signal The clock circuit (114) is configured to provide the first clock signal to the first clock input of the DDFS (116) at a frequency that is based on a selected channel.