| 摘要 |
PURPOSE: A duty cycle correction circuit capable of generating an output clock pair having a constant duty ratio is provided to perform high speed operation, low power consumption, wide duty correction range, and an excellent jitter property. CONSTITUTION: A duty cycle correction circuit capable of generating an output clock pair having a constant duty ratio includes a feedback circuit, a first input node(110), and a second input node(120). The feedback circuit generates a first control signal pair and a second control signal pair based on the output clock pair. The first input node corrects a duty ratio of the input clock pair in response to the first control signal pair. The second input node corrects a duty ratio of a clock pair outputted from the first input node in response to the second control signal pair. |
