发明名称 SEMICONDUCTOR PACKAGE AND SUBSTRATE USED FOR THE SAME
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a semiconductor package restraining warpage in the side of a substrate, preventing fracture in the substrate, and avoiding damage to the surface of a chip and the side, and to provide a substrate used for the semiconductor package. <P>SOLUTION: The substrate 210 of the semiconductor package 200 includes a plurality of signal fingers 211, a dummy metal pattern 212, and at least one peripheral recessed groove 213 passing through the substrate 210. The dummy metal pattern 212 is extended to a position 213 of the peripheral recessed groove, and is electrically insulated from the signal finger 211. The chip 220 is installed on the substrate 210 and includes a plurality of bonding pads 221, 222, and electrically connects the bonding pad of the chip to the signal finger 211 of the substrate via an electric connection element 230. A sealing body 240 seals the electric connection element 230 and is filled into the peripheral recessed groove 213. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2009200210(A) 申请公布日期 2009.09.03
申请号 JP20080039711 申请日期 2008.02.21
申请人 POWERTECH TECHNOLOGY INC 发明人 FAN WEN-JENG;LIU YI-LING
分类号 H01L23/12 主分类号 H01L23/12
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