发明名称 |
ELECTRICAL ERASABLE PROGRAMMABLE MEMORY TRANSCONDUCTANCE TESTING |
摘要 |
A test method determines if an array (103) of a Flash EEPROM circuit (101) has a bit cell (105, 107, 109, 111) with a transconductance (gm) that is deficient. The method preconditions all bit cells (403, 405, 407) of the array to a particular programmed state and then determines whether any of the bit cells exhibit undesirable operating characteristics by reading (411) each bit cell to determine (413) whether its transconductance is less than desirable.
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申请公布号 |
WO2009085722(A3) |
申请公布日期 |
2009.09.03 |
申请号 |
WO2008US86915 |
申请日期 |
2008.12.16 |
申请人 |
FREESCALE SEMICONDUCTOR INC.;EGUCHI, RICHARD K.;HE, CHEN;SYZDEK, RONALD J. |
发明人 |
EGUCHI, RICHARD K.;HE, CHEN;SYZDEK, RONALD J. |
分类号 |
G06F11/22;G06F11/26;G06F11/263 |
主分类号 |
G06F11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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