发明名称 ERROR CORRECTION DECODER
摘要 PROBLEM TO BE SOLVED: To provide an error correction decoder capable of improving a coding gain by a simple configuration. SOLUTION: The error correction decoder includes a delay element 12, a soft decision Viterbi decoder 5, a deinterleaver 15, a hard decision Reed-Solomon decoder 10 and interleavers 20a and 20b. The soft decision Viterbi decoder 5 receives the input of a reception sequence (X, Y) and generates decoding data TSP which are hard output. Then, the hard decision RS decoder 10 receives the output result of the soft decision viterbi decoder 5 through the deinterleaver 15 and performs hard decision RS decoding. The hard decision RS decoder 10 generates decoding data and decoding auxiliary information, and feeds back the generated decoding result through the interleavers 20a and 20b to the soft decision viterbi decoder 5. Thus, repetitive decoding is executed. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009200732(A) 申请公布日期 2009.09.03
申请号 JP20080039185 申请日期 2008.02.20
申请人 SYNTHESIS CORP 发明人 MURATA SHINICHI;SEKIGUCHI TAKAO;MIZUSAWA HIDEYUKI
分类号 H03M13/29 主分类号 H03M13/29
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