| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device whose pattern layout is optimized so that the yield of flattening by CMP is not influenced owing to increase of the integration degree of the semiconductor device having a well contact diffusion layer and a sub-contact diffusion layer disposed between both P- and N-channel transistor arrays arranged facing each other. SOLUTION: In a semiconductor device in which a well contact diffusion layer pattern 13 and a sub-contact diffusion layer pattern 14 are arranged in a dotted form between a P-ch transistor diffusion layer pattern 11 and an N-ch transistor diffusion layer pattern 12 and a dummy pattern 15 for CMP is disposed around the P-ch and N-ch transistor arrays, the data rate exceeds 75% when the well contact and sub-contact diffusion layer patterns are respectively arranged in a line and is in a range of 25% to 75% when they are arranged in a dotted form. COPYRIGHT: (C)2009,JPO&INPIT
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