| 摘要 |
A complementary metal oxide semiconductor (CMOS) imager flush reset circuit is provided. The flush reset circuit has an interface to receive first (e.g., VDD) and second (e.g., ground) reference voltages. The flush reset circuit has a solitary (flush) signal interface. There is also an interface connected to a transistor set power interface to supply a Vflush1 signal at least one threshold voltage different than the second reference voltage, in response to receiving a flush signal. The flush signal is used to create a CMOS imager hard reset prior to a soft reset.
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