发明名称 AUTOMATIC ARRANGEMENT/WIRING METHOD, AND SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide an automatic arrangement/wiring method capable of correcting arrangement of wiring, and uniformizing a distribution of vias while reducing cost and improving ease of manufacturing. SOLUTION: This automatic arrangement/wiring method is composed such that a plurality of vias v are arranged laterally and horizontally at certain intervals in the whole or a part of a target region of automatic arrangement/wiring between wiring layers; wirings M2s and M1s of the wiring layers are arranged to pass among the plurality of vias v; and ends of the wirings M2s and M1s are connected to vias vs, vA and vB in the vicinities of the ends. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009200309(A) 申请公布日期 2009.09.03
申请号 JP20080041385 申请日期 2008.02.22
申请人 RENESAS TECHNOLOGY CORP 发明人 NISHIDA HIROKI
分类号 H01L21/82;G06F17/50 主分类号 H01L21/82
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