| 摘要 |
PROBLEM TO BE SOLVED: To provide a verification apparatus of a semiconductor integrated circuit for verifying a function at a high speed. SOLUTION: The verification apparatus comprises: a clock period extracting section 11 for extracting period information on a plurality of clocks having different periods in a to-be-verified circuit from a net list 1 and a timing constraint file 2 of the to-be-verified circuit 3; a base clock waveform generating section 12 for calculating the least common multiple of the periods of a plurality of the clocks, obtaining the number of cycles of each clock included in the least common multiple, and generating a base clock waveform; a clock edge list generating section 13 for calculating an occurrence time of a rising event and a falling event of each clock in the base clock waveform, ; and a circuit description generating section 14 for assigning the event of each clock to rising of a hardware system clock in order of the occurrence time, and generating a circuit description of a clock generating circuit for generating a verifying clock corresponding to each clock. COPYRIGHT: (C)2009,JPO&INPIT
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