发明名称 INTEGRATED CIRCUIT, OPERATION TEST METHOD THEREFOR AND OPERATION TEST PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide an integrated circuit which can make its operation test solely by itself. SOLUTION: The integrated circuit 1 is an integrated circuit to constitute a semiconductor memory 100 through connection with semiconductor memories 9. It has a BIST (Built-In Self-Test) circuit 3 to produce a write request 301 containing dummy data 303 when a start signal is applied from the outside, a memory control circuit 6 to output the dummy data as the write data in response to the write request, and a read data selector circuit 10 to loop back the write data to the memory control circuit. The memory control circuit has a register 31 to hold the write data looped back by the read data selector circuit, and outputs a defect signal by finding out trouble in regular operation. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009199703(A) 申请公布日期 2009.09.03
申请号 JP20080043045 申请日期 2008.02.25
申请人 NEC COMPUTERTECHNO LTD 发明人 SUZUKI EIJI
分类号 G11C29/12;G11C29/42 主分类号 G11C29/12
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