MOS TRANSISTOR CIRCUIT EMPLOYING DOUBLE INSULATED GATE FIELD EFFECT TRANSISTOR, CMOS CIRCUIT EMPLOYING THE SAME, SRAM CELL CIRCUIT, CMOS-SRAM CELL CIRCUIT, AND INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide an MOS transistor circuit employing a double insulated gate field effect transistor (FET) in which high-speed operation of a unit circuit is made compatible with reduction of power consumption during out-of-use (annotation), at a normal time, or on standby, a CMOS transistor circuit employing the same, SRAM cell circuit, CMOS-SRAM cell circuit, and integrated circuit. SOLUTION: In the MOS transistor circuit constituted of a four-terminal double insulated gate FET, one gate 1 of the four-terminal double insulated gate FET is used as an input terminal, one terminal of a resistor Rg is connected to another gate 2, a source is connected to a first power source, a drain is used as an output terminal and connected through a load element to a second power source, and another terminal of the resistor is connected to a third power source of a fixed potential. COPYRIGHT: (C)2009,JPO&INPIT