| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL circuit capable of preventing the erroneous recognition of a deadlock state when activating oscillation and returning to a normal lock state even when falling into the deadlock state after the oscillation activation is ended. <P>SOLUTION: The PLL circuit includes: a deadlock detection circuit 70 for detecting that the PLL circuit 1 falls into the deadlock state, and controlling control signals UPI and DOUN1 output from a phase comparator 10 so as to lower the voltage level of control signals CNT for controlling the oscillation frequency of the output signals OUT of a voltage controlled oscillator 50; and an activation detection circuit 80 for detecting that feedback signals DivCLK from a logic circuit 60 exceeds the threshold frequency from the state of being at a frequency less than the prescribed threshold frequency and operating the deadlock detection circuit 70. <P>COPYRIGHT: (C)2009,JPO&INPIT |
