| 摘要 |
PROBLEM TO BE SOLVED: To provide a logic verification device which achieves simple and efficient debugging. SOLUTION: The logic verification device 10 includes: an FPGA (Field Programmable Gate Array) 2 which is mounted on a substrate 1 and can dynamically rewrite an internal circuit; a configuration memory 3 which is mounted on the substrate 1 and in which configuration data 300 comprising an RTL (Register Transfer Level) which becomes data to dynamically reconfigure the internal circuit of the FPGA 2 corresponding to the FPGA 2, and a wrapper RTL is stored; a PLD (Programmable Logic Device) identification information holding part 4 which is mounted on the substrate 1 corresponding to the FPGA and outputs the PLD identification information uniquely corresponding to the FPGA 2 to the FPGA 2; and a first output part 6 which is mounted on the substrate 1 corresponding to the FPGA 2 and outputs a result of determination by the FPGA 2 based on the PLD identification information. A wrapper RTL of the configuration data 300 has RTL identification information uniquely corresponding to the RTL of the configuration data 300, and also has a determination function to compare the RTL identification information with the PLD identification information to determine existence of difference. COPYRIGHT: (C)2009,JPO&INPIT
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