| 摘要 |
The direct access memory is composed of n memory arrays (1.1 to 1.n), of the address decoder (2), of the data connecting circuit (3), and of the write controlling circuit (4). The address decoder (2) consists of the binary decoder (5) and of n-1 selectors (6.1 to 6.n-1). The outer interface of the memory consists of the address bus (01) for the address input, of k data buses (02.1 to 02.k) for data transmission, and of the control bus (03) for the write control. The data is stored by bytes with every data byte D being addressable by one address A. After address the A setting on the address bus (01), in memory arrays (1.1 to 1.n) the memory locations are activated in which the data bytes DA, DA+1,..., DA+k-1 are stored. The data connecting circuit (3) connects the data interfaces of the memory arrays (1.1 to 1.n) with the data buses (02.1 to 02.k) so that the first data bus (02.1) transmits the data byte DA, and simultaneously the second data bus (02.2) transmits the data byte DA+1,..., and simultaneously, the kth data bus (02. k) transmits the data byte DA+k-1. In one write/read cycle, by this the memory provides the parallel access to sequentially arranged data which is several bytes long, e.g. to the instruction code, said data being stored in an arbitrary memory location. |
