| 摘要 |
A circuit for a read mask test and a control method thereof are provided to control a read mask operation of a byte unit and to generate a latency signal by using a top side data mask signal in a read mask operation. A first command generator(110) generates a first command by assembling a read operation pulse signal with a bottom side data mask signal on a read mask test mode. A second command generator(120) generates a second command by assembling a read operation pulse signal with a top side data mask signal on a read mask test mode. A latency signal generator generates a latency signal synchronized to a DLL clock in a command generation time of the command generator. A read mask test operation controller controls a data read mask test operation into a byte unit through a latency signal generated in the latency signal generator. |
