发明名称 RECONFIGURABLE LOAD-REDUCED MEMORY BUFFER
摘要 A memory module can include a data buffer having a data bus interface and a dynamic random access memory (DRAM) coupled to the data buffer. The memory module may also include a switch connected in parallel with the data buffer, wherein the switch can selectively bypass the data buffer. In one example, the memory module also includes a registered buffer having an address bus interface, where the switch may selectively bypass the data buffer based on a program signal obtained from an address bus via the address bus interface.
申请公布号 US2011138162(A1) 申请公布日期 2011.06.09
申请号 US20090632919 申请日期 2009.12.08
申请人 CHIU SCOTT;ARAFA MOHAMED 发明人 CHIU SCOTT;ARAFA MOHAMED
分类号 G06F9/24;G06F1/26;G06F12/02;G11C7/00;G11C7/10 主分类号 G06F9/24
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