| 摘要 |
PROBLEM TO BE SOLVED: To secure the efficiency of stable data transfer on a data bus. SOLUTION: This cache memory control device includes: a plurality of data memories 2A each storing data as a cache memory 2; a plurality of data buses 6 for transferring the data from the data memories 2A to cores 3; an instruction execution part 51 accessing each data memory 2A according to a period time-shared in each data memory 2A, and transferring the read data to the data bus 6 corresponding to the core 3; an instruction input part 52 putting an access instruction into the instruction execution part while inhibiting an input of a subsequent access instruction to the same period within a pipe input inhibition period and inhibiting an input of subsequent access using the same bus as a preceding access instruction in a bus sharing inhibition section; and a timing control part 53 controlling the instruction execution part 51 so that timing to start the transfer of the data corresponding to the subsequent access instruction to the bus is delayed when the subsequent access instruction using the same bus in a pipe input inhibition section is put in. COPYRIGHT: (C)2011,JPO&INPIT
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