| 摘要 |
PROBLEM TO BE SOLVED: To provide a level shift circuit capable of suppressing deterioration in characteristics even when driven at the maximum value within the rated range of a power supply voltage. SOLUTION: The level shift circuit 2A includes a first input terminal 11, second input terminal 12, third input terminal 13, first output terminal 21, second output terminal 22, first PMOS transistor 31, second PMOS transistor 32, first NMOS transistor 41, second NMOS transistor 42, first buffer circuit 51A, second buffer circuit 52A, and first inverter circuit 60. The first buffer circuit 51A is configured such that an inverter circuit at a previous stage constituted of a PMOS transistor QP<SB>11</SB>and an NMOS transistor QN<SB>11</SB>, and an inverter circuit at a post stage constituted of a PMOS transistor QP<SB>12</SB>and an NMOS transistor QN<SB>12</SB>are subjected to cascade connection, and further includes a PMOS transistor QP<SB>13</SB>. COPYRIGHT: (C)2011,JPO&INPIT
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