| 摘要 |
An inverter having three phase modules with an upper valve arm and a lower valve arm having each at least three two-pole subsystems connected in series, which each subsystem having a storage capacitor, is controlled in the event of failure of one or more subsystems by setting the terminal voltage of the failed subsystems permanently to zero, setting the terminal voltage of a corresponding number of fault-free subsystems in corresponding fault-free valve branches likewise to zero, and increasing the capacitor voltages of the fault-free subsystems of the failed valve branches such that their sum is equal to the sum of the capacitor voltages of the subsystems of a corresponding fault-free valve branch, while leaving the control of the fault-free phase modules unchanged. In this way, a symmetrical voltage system with maximum amplitude is obtained at the inverter outputs.
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