发明名称 POWER-ON CLEAR CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a power-on clear circuit for generation and output of a clear signal which is not affected by a rising state of a power supply voltage. SOLUTION: A power-on clear circuit of the present invention includes: a pulse generating circuit 1 which generates a pulse by powering-on; a delay circuit 5 which delays and outputs the generated pulse; two-stages of cascaded inverters 6, 7 to which the delayed pulse is input; and a NOR circuit 8 having an input terminal, to which an output from a front-stage side of the delay circuit 5 is input, and an input terminal to which an output from the first stage of inverter 6 is input. The output of the NOR circuit 8 is regarded as a first clear signal which is not affected by a rising state of a power supply voltage, and the output of the inverter 7 is regarded as a second clear signal corresponding to the rising state of the power supply voltage. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011114754(A) 申请公布日期 2011.06.09
申请号 JP20090271160 申请日期 2009.11.30
申请人 SEIKO NPC CORP 发明人 KOZASA HIROYUKI
分类号 H03K17/22;G06F1/24 主分类号 H03K17/22
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