| 摘要 |
PROBLEM TO BE SOLVED: To provide an information processor which has a plurality of CPUs each connected to a bus via bus bridges, and includes a bus arbiter for arbitrating data transmission/reception of the bus bridges using the bus, while allowing addition and change of CPUs without significantly changing the design. SOLUTION: In an information processor 100, CPUs 0 and 1 are connected to a bus arbiter 12 via bus bridges 10 and 11, and the bus arbiter 12 is connected to a local bus 20. The bus bridges 10 and 11 include exception handling storage parts 101 and 111 storing exception handling addresses and the like. The CPU 1, for example, can acquire the exception handling addresses and the like by only data transmission and reception to/from the bus bridge 11. Therefore, a CPU can be added or changed without significantly changing the configurations of the local bus 20, the bus arbiter 12, and the like by only adding or changing the bus bridge 11 and the CPU 1 connected to it. COPYRIGHT: (C)2011,JPO&INPIT
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