| 摘要 |
The system according to the invention comprises at least two power semiconductor chips (1, 2, 3, 4) being connected in parallel and comprising each a gate terminal for switching the power semiconductor chip (1, 2, 3, 4) in a blocking- state by a first gate voltage and for switching the power semiconductor chip (1, 2, 3, 4) in a conducting- state by a second gate voltage. The system comprises further a control means (16, 57) adapted for applying the first or the second gate voltage to the gate terminals of the at least two power semiconductor chips (1, 2, 3, 4). The control means (16) is adapted for applying a third gate voltage to the gate terminal of the at least one remaining power semiconductor chip (1, 2, 3, 4) when a power semiconductor chip (1, 2, 3, 4) fails, and that the third gate voltage is higher than the second gate voltage. |
